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Sr. Verification Engineer, FPGA Core Networking

Job ID: 1909802 | Amazon Kuiper Manufacturing


Job summary
Project Kuiper is a new initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world.

Come join us at Amazon!

The Role:
Create FPGA solutions to support Amazon Project Kuiper’s satellite communication system. This is a unique opportunity to define a groundbreaking new system with few legacy constraints. The Sr FPGA verification engineer will work with systems teams to define/develop/implement/test/release FPGA test environments in order to verify FPGA based solutions to enable Project Kuiper. This will focus on verifying digital designs for networking functions using the latest generations of FPGA technologies and modern FPGA design processes and tools.
In this role you will:
• Plan, architect, develop, and use configurable, self-checking testbenches implemented in SystemVerilog/UVM
• Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions
• Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases;
• Enhance your leadership skills while leading small to medium sized DV teams
• Create reusable Verification IP to be shared across the organization;
• Drive changes to our process and methodologies.
• Enhance your DV skills as well as your knowledge of Networking while working with subject matter experts;
• Mentor junior engineers across multiple U.S. locations

Export Control Requirement:
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.


  • Bachelor's degree in Electrical Engineering, related discipline, or 10 + years of FPGA experience
  • 3+ years of experience in FPGA design & implementation
  • 3+ years of experience with System Verliog RTL coding
  • 3+ year of experience in the design, test, delivery, support of multiple FPGAs shipping to customers
  • 3+ years of experience with modern ASIC / FPGA design and verification tools


  • Bachelor's degree in Computer Engineering/Science, Electrical Engineering, related discipline, or equivalent experience
  • 10+ years of experience in FPGA/ASIC design verification
  • Experience planning, architecting, developing, and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM
  • Experience developing and implementing test plans.
  • Experience with FPGA/ASIC design and verification tools (Synopsys, Mentor Questa, Cadence)
  • Experience monitoring and optimizing design verification coverage wrt to line, FSM, functional, etc.
  • Experience deploying System Verilog Assertions to enhance verification and reduce debug time
  • Strong communication and documentation skills
  • Working knowledge of Ethernet, Interlaken, PCI Express, SPI, UART, and I3C protocols
  • Understanding of TCP/IP Networking with specific familiarity of OSI layers 2-4

Preferred qualifications

The following skills/experience are preferred, but not required:
• Git/Jira/BitBucket
• Shell scripting/C++/Python
• FPGA Design Experience
• Experience creating reusable Verification IP.
• Experience leading small to medium teams with accountability for cost, schedule, and quality
• Experience driving process.
• Demonstrated mentoring skills

Amazon is an Equal Opportunity Employer – Minority / Women / Disability / Veteran / Gender Identity / Sexual Orientation / Age

Amazon is committed to a diverse and inclusive workplace. Amazon is an equal opportunity employer and does not discriminate on the basis of race, national origin, gender, gender identity, sexual orientation, protected veteran status, disability, age, or other legally protected status. For individuals with disabilities who would like to request an accommodation, please visit